1. Field of the Invention
The present invention relates to a solid-state imaging device and a method of manufacturing the same, and particularly to a solid-state imaging device including within a pixel a unit for converting electric charge generated by a photoelectric converting unit into a pixel signal, for example, a CMOS (complementary metal-oxide semiconductor) image sensor and a method of manufacturing the same. The CMOS image sensor is herein described as an image sensor formed by either applying a CMOS process or partly using the CMOS process. Further, the present invention relates to a camera module incorporating the solid-state imaging device.
2. Description of the Related Art
The CMOS image sensor is a solid-state imaging device including a plurality of pixels formed of a photoelectric converting element and a plurality of MOS (metal-oxide semiconductor) transistors, the pixels being arranged in the form of a two-dimensional array, in which electric charge generated by the photoelectric converting element is converted into a pixel signal and read. In recent years, such CMOS image sensor has been a focus of constant attention as an imaging element used for electronic equipment such as a built-in camera for a mobile phone unit, a digital still camera and a digital video camera.
FIG. 1 shows a schematic arrangement of a typical CMOS image sensor (image sensor chip). As shown in FIG. 1, a CMOS image sensor 1 includes in a semiconductor substrate (semiconductor chip) a pixel array block (imaging area) 2, and as a peripheral circuit portion, a vertical driving circuit 3, a shutter driving circuit 4, a CDS (correlated double sampling) circuit 5, a horizontal driving circuit 6, an AGC (automatic gain control) circuit 7, an A/D (analog-to-digital) converter (A/D converting circuit) 8, a timing generator 9 and the like.
As shown in FIG. 1, the pixel array block 2 includes a plurality of pixels in the form of two-dimensional arrays, each pixel including one or a plurality of photoelectric converting elements and MOS (metal-oxide semiconductor) transistors; output signal lines from respective pixels; and a plurality of signal lines to drive respective pixels. The vertical driving circuit 3 supplies to the pixel array a signal to select a read row of pixels. The shutter driving circuit 4 is provided to select a row similarly to the vertical driving circuit 3 and can adjust time (storage time) for exposing the photoelectric converting element by adjusting a time interval with the vertical driving circuit 3.
A signal read from the row selected by the vertical driving circuit 3 is input to the CDS circuit 5 provided for each column or a plurality of columns. The CDS circuit 5 receives a reset level and a signal level from each pixel and cancels a fixed pattern noise of each pixel by calculating a difference between the reset level and the signal level. The horizontal driving circuit 6 sequentially selects signals on which CDS processing is performed and which are retained in respective columns. A signal of the selected column is supplied to the AGC circuit 7 at the subsequent stage, applied with a proper gain, converted into a digital signal by the A/D converter 8 and then output to the outside of the image sensor chip. Further, respective circuit blocks (the vertical driving circuit 3, the shutter driving circuit 4, the CDS circuit 5, the horizontal driving circuit 6, the AGC circuit, the A/D converter 8 and the like) are driven by signals generated inside the timing generator 9.
The block arrangement illustrated in FIG. 1 shows an example of the CMOS image sensor. Other CMOS image sensors such as a CMOS image sensor not including an A/D converter inside the chip, a CMOS image sensor including A/D converters in respective columns, a CMOS image sensor including a single CDS circuit, a CMOS image sensor including a number of output systems such as a CDS circuit, an AGC circuit and the like may also be used. Signals are read from the pixels to the CDS circuit 5 through the pixel output line 10 provided to each column.
FIG. 2 shows an example of a pixel and peripheral circuit portion of the above-described CMOS image sensor. As shown in FIG. 2, a CMOS image sensor 21 includes a pixel array block (imaging area) 24 formed of a two-dimensional array of a plurality of pixels (unit cells) 23 each including one photoelectric converting element 22 made of a photo-diode, for example, and a plurality of MOS transistors and a peripheral circuit portion.
The photoelectric converting element 22 receives light and stores signal electric charges generated by photoelectric conversion. A plurality of MOS transistors are provided for each pixel and in this example there are four transistors, specifically, a transfer transistor 26, a reset transistor 27, an amplification transistor 28 and a selection transistor 29. The transfer transistor 26 transfers signal electric charges stored in the photoelectric converting element 22 to a floating diffusion (FD), in other words, the gate of the amplification transistor 28. The reset transistor 27 resets gate potential of the amplification transistor 28. The amplification transistor 28 amplifies signal electric charges. The selection transistor 29 selects the output pixel.
In the pixel 23, the source of the transfer transistor 26 is connected to the photoelectric converting element 22 and the drain thereof is connected to the source of the reset transistor 27. A transfer signal line 31 for the control of gate potential is connected to the gate of the transfer transistor 26. The drain of the reset transistor 27 is connected to a power source potential supply line 30 and the gate thereof is connected to a reset signal line 32 to control the gate potential. The drain of the amplification transistor 28 is connected to the power source potential supply line 30, the source thereof is connected to the drain of the selection transistor 29 and the gate thereof is connected to the floating diffusion (FD) between the transfer transistor 26 and the reset transistor 27. The source of the selection transistor 29 is connected to the pixel output line 34 and the gate thereof is connected to the selection signal line 33 to control the gate potential.
A transistor 36 to supply a constant electric current is connected to the pixel output line 34, and supplies a constant electric current to the selected amplification transistor 28, causing the amplification transistor 28 to operate as a source-follower transistor and to output to the pixel output line 34 a gate potential of the amplification transistor 28 and a potential having a constant voltage difference from the potential of the amplification transistor 28. A constant electric potential supply line 37 for supplying a constant electric potential is connected to the gate of the transistor 36, allowing the transistor 36 to perform a saturation region operation of supplying a constant electric current.
On the other hand, a vertical selector 41, a column selector 42 and a CDS (correlated double sampling) circuit 43 are located as peripheral circuits. Further, a row selection AND element 45, output end of which is connected to the transfer signal line 31; a row selection AND element 46, output end of which is connected to the reset signal line 32; and a row selection AND element 47, output end of which is connected to the selection signal line 33, are provided to each row of the pixels 23.
One input end of the row selection AND element 45 of each row is connected to a pulse terminal 48 configured to supply a transfer pulse to the transfer signal line 31, and the other input end thereof is connected to an output from the vertical selector 41. One input end of the row selection AND element 46 of each row is connected to a pulse terminal 49 configured to supply a reset pulse to the reset signal line 32, and the other input end thereof is connected to an output from the vertical selector 41. One input end of the row selection AND element 47 of each row is connected to a pulse terminal 50 configured to supply a selection pulse to the selection signal line 33, and the other input thereof is connected to an output from the vertical selector 41.
According to the above-mentioned arrangement, each control pulse is supplied only to the signal line selected by the vertical selector 41. An operation of reading from each pixel 23 is carried out as follows together with drive signals shown in FIG. 3.
As shown in FIG. 3, a transfer signal (pulse) S1 is supplied to the transfer signal line 31, a reset signal (pulse) S2 is supplied to the reset signal line 32 and a selection signal (pulse) S3 is supplied to the selection signal line 33.
First, the selection pulse S3 and the reset pulse S2 are supplied. The selection transistor 29 of the row to be read and the reset transistor 27 are ON, and electric potential of the gate (floating diffusion FD) of the amplification transistor 28 is reset. After the reset transistor 27 is OFF, a voltage corresponding to reset level of each pixel 23 is read to the CDS circuit 43 at the subsequent stage. Next, the transfer pulse S1 is supplied, and the transfer transistor 26 is ON to transfer electric charges stored in the photoelectric converting element 22 to the floating diffusion (FD), in other words, the gate of the amplification transistor 28. After the transfer of the electric charges, the transfer transistor 26 is OFF and a voltage of a signal level corresponding to the amount of stored electric charges is read to the CDS circuit 43 at the subsequent stage.
The CDS circuit 43 calculates a difference between the previously read reset level and the signal level and cancels a fixed pattern noise due to variations of a threshold voltage Vth of the amplification transistor 28 for each pixel. When the signal stored in the CDS circuit 43 is selected by the column selector 42, the selected signal is read through a horizontal signal line 44 to circuits at the subsequent stages such as an AGC (automatic gain control) circuit to be processed.
FIG. 4 is a diagram showing a schematic cross-sectional structure of the pixel array block 2 shown in FIG. 1. In the pixel array portion, a plurality of photoelectric converting elements 22 corresponding to respective pixels is formed on a semiconductor substrate 51. While FIG. 4 shows only the photoelectric converting elements 22, the other MOS transistors 26, 27, 28 and 29 described above are formed on respective pixels. A plurality of wiring layers, in this example, three wiring layers 53, 54 and 55 are formed above the semiconductor substrate 51 through an insulating interlayer 52. These wiring layers correspond to the vertical signal line 34, the reset signal line 32, the transfer signal line 31, the selection signal line 33, the power supply line 30 and connecting electrodes (connecting respective signal lines and MOS transistors) provided independently of those lines 30 to 34.
Here, the signal lines (34, 32, 31, 33 and connecting electrodes) in the horizontal and vertical directions are arranged so as to form an opening portion around the photoelectric converting element 22. The power source wiring line 30 corresponds to the third wiring layer 55 and is formed on the uppermost layer. As shown in FIG. 5, the wiring layer 55 to be the power supply line 30 is formed to have openings 61 corresponding to the photoelectric converting elements 22 [220, 221, 222, . . . ]. These wiring layers 53 to 55 also can serve as light-shielding layers as well. A color filter 63 is formed on an insulating interlayer of the uppermost layer, that is, a planarized film 62, and an on-chip microlens 64 is formed on the color filter 63.
At present, solid-state imaging devices typically include the on-chip microlens in order to improve an optical focusing ratio as described above. However, in the peripheral portion where light is incident obliquely on the imaging area, the center of light focused by the on-chip microlens is shifted from the center of the photoelectric converting element. Therefore, the optical focusing ratio is lowered, thereby lowering sensitivity. Such decrease in sensitivity is larger in the peripheral portion of the imaging area as compared to the center thereof and causes “shading” as a result. Therefore, the on-chip microlens is shifted in order to control such shading.
Also, since the CMOS solid-state imaging device includes a plurality of wiring layers, incident light is shaded by the wiring layers to cause shading. Since a CCD (charge-coupled device) solid-state imaging device has a structure different from that of the CMOS solid-state imaging device, the incident light is not shaded by the wiring layers. Japanese Unexamined Patent Application Publication No. 2004-253568 and Japanese Unexamined Patent Application Publication No. 2003-273342 have proposed technologies of controlling shading by also shifting the wiring layers.